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STATus:QUEStionable:ENABle <enable_value>
STATus:QUEStionable:ENABle?
Enables bits in the enable register for the
reported to the Status Byte. An enable register defines which bits in the event register will be reported to
the Status Byte register group. You can write to or read from an enable register.
A decimal value that corresponds to the binary-weighted sum of the bits in the
register.
Enable bit 9 (decimal value 512) in the enable register.
Use the <enable> parameter to specify which bits will be reported to the Status Byte. The decimal
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value specified corresponds to the binary-weighted sum of the bits you wish to enable in the register.
For example, to enable bit 0 (decimal value = 1), bit 1 (decimal value = 2) and bit 12 (decimal value =
4096), the corresponding decimal value would be 4099 (1 + 2 + 4096).
A
STATus:PRESet
clears all bits in the enable register.
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The <enable> setting is nonvolatile; it does not change after a Factory Reset (*RST) , Instrument Pre-
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set (SYSTem:PRESet), Status Preset (STATus:PRESet) or Clear Status (*CLS).
The
*PSC
command controls whether the enable register is cleared at power on.
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STATus:QUEStionable[:EVENt]?
Returns the event register for the
register that latches events from the condition register. While an event bit is set, subsequent events cor-
responding to that bit are ignored. The register bits are cleared when you read the register.
Parameter
Typical Return
(none)
+1024
Read the event register (bit 10 is set):
STAT:QUES?
Once a bit is set, it remains set until cleared by reading the event register or by sending
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status).
Keysight Truevolt Series Operating and Service Guide
Questionable Data Register
Parameter
Questionable Data Register
SCPI Programming Reference
group. The selected bits are then
Typical Return
+512
group. An event register is a read-only
*CLS
(clear
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