Cardin Elettronica MORPH433W01 Mode D'emploi page 23

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Frame make up for the WIEGAND signals
The frame in the WIEGAND format is emitted by means of the DATA0 and DATA1 signals. The dura-
tion of each single bit is 50μs while the waiting period between one bit and the next is 2 ms.
Parity B4 B3 B2 B1 Character
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
Frame construction example limited to six characters; transmitting the code "452"
MEANING
BIT
Start
1 0 1 1
"4"
0 1 0 0
"5"
0 1 0 1
"2"
0 0 1 1
End
1 1 1 1
LRC
0 1 1 1
Frame composition diagrams for ISO2 signals
There are three ISO2 signals: CLS (Card Loading Signal), RCP (Read Clock Pulse) and RDP (Read
Data Pulse). The 3 signals are active low.
First of all the CLS drops and after 5 ms 10 clock pulse are sent; the data packet is then sent and
then their is a pause of 5ms before pulling up the CLS.
1
DATA 1
DATA 0
ISO2 PROTOCOL (BIT FLOW SEQUENCE)
The frame leaving the interface is formed of 16 characters. Each
0
character is made up of 5 bits according to the table on the left,
1
where the most significant bit is B4, and the least significant is
2
B1.
3
4
The parity bit is odd parity for B4, B3, B2, B1.
5
6
7
The frame is as follows: START + CHANNEL (1 character) + SEP
8
+ CODE (10 characters) + SEP + END + LRC, i.e. 16 characters
9
altogether.
START
SEP
END
PARITY
0
At the end of the frame an LRC control character is sent which
0
is calculated by working out the even parity longitudinally along
1
the corresponding bits as shown in the table on the left.
0
The first bit out is B1 and the last one out is the parity bit.
1
0
CLS
RCP
RDP
5ms
0
2mS
5ms
23
1

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